The present invention is directed to digital radio receivers which utilize analog to digital conversion of received analog signals. Specifically, a continuous time delta sigma analog to digital converter is disclosed for producing a high resolution digital signal having a low phase noise floor.
Digital radio receivers provide for enhanced signal processing by converting received analog radio signals into digital signals. Digital processing is very sophisticated, and through the use of various processing algorithms. distortions due to intersymbol interference can be significantly reduced.
In processing digital radio signals, the higher up in the frequency conversion chain that signals are digitized, the more dynamic range and resolution is required for the analog to digital converter. Broadband digitization must not generate noise or frequency artificats in the adjacent channels. At the same time, it is necessary to digitize the entire bandwidth imposing significant design contraints in terms of linearity and resolution on the analog to digital converter. One type of analog to digital converter which addresses these needs is the continuous time delta sigma analog to digital converter (CT delta-signal ADC). A CT delta-sigma ADC provides high resolution digitizing of an analog signal with a very high oversampling rate. Eighteen to twenty bits of resolution can be achieved if each analog signal being received is oversampled 128 to 256 times. These high resolutions are achieved by noise shaping the input signal through a loop filter, and then oversampling the filtered signal with an analog to digital converter (ADC). The CT delta sigma ADC requires a clock signal rate to achieve the required oversampling ratio. This approach works well for bandwidths in the 1 to 10 KHz range. As the bandwidth of the input signal increases from the 10 KHZ region to a higher 1 GHZ region, the clock rate must be correspondingly increased to achieve the same oversampling ratio. As the clock rate for sampling the incoming analog signal increases to above 1 GHZ, in order to sample a 30 MhZ bandwidth signal, the phase jitter increases the noise floor limiting the digital signal resolution.
A significant source of phase jitter occurs in the CT delta-sigma ADC feedback path. In conventional CT delta-sigma ADC architecture, an analog feedback signal is created by reconverting the digital signal to an analog signal. Phase jitter of the clock signal of the digital to analog converter creates a noise function which reduces the CT delta-sigma ADC resolution.
The design of the DAC introduces other significant problems for maintaining both linearity and a low phase noise contribution to the feedback signal. The DAC may either be a return to zero (RZ) DAC or a non return to zero (NRZ) DAC. Each of these approaches has their own problems. For instance, an RZ DAC output signal will have a higher frequency content than the NRZ DAC and a greater jitter problem. Additionally, the output of the DAC in the feedback loop does not track the input signal very well. A large error voltage is generated and the input summing junction which combines the feedback signal and input signal must have a high degree of linearity to avoid generating undesired frequency artifacts in the analog signal frequency bandwidth. The NRZ DAC, however, has a higher linearity problem than the RZ DAC given the fact that the amount of energy transferred to the output changes during a data transition. RZ DAC architecture has the benefit over NRZ architecture of transferring the same amount of energy irrespective of the data transitions. The present invention makes significant improvements in the CT delta-sigma ADC design to minimize these performance limitations.
In accordance with the invention, a continuous time (CT) delta-sigma analog to digital converter is provided. The CT delta-sigma ADC operates at a high oversampling rate to provide a high degree of resolution of an input analog signal. A summing junction receives the analog signal as well as a feedback signal, producing an error signal which is filtered and converted into a multi-bit digital signal. The feedback signal which is combined with the input analog signal is generated from a sin DAC which reconverts the multi-bit digital signal to an analog signal, producing a feedback signal having a reduced phase jitter and a correspondingly lower noise floor to the summing junction.
In carrying out the invention in accordance with a preferred embodiment, a NRZ sin DAC is utilized as the feedback DAC which voids a significant contribution of phase noise, and has a constant energy output substantially independent of the data transitions of the digital data. The NRZ DAC comprises first and second sin DACs which convert the digital data to a RZ analog signal. The RZ sin DAC signals are out of phase, and when combined, produce an NRZ signal output. The NRZ signal is provided as a feedback signal to the input summing junction. Thus, it is possible to achieve minimum phase noise contribution due to clock jitter, while at the same time avoiding the consequences of an RZ feedback signal which generates frequency artifacts due to the nonlinearity of the input summing junction.